Welcome to AnvilHDL Documentation!
Anvil is a general-purpose hardware description language (HDL) that statically guarantees timing safety – the absence of timing hazards, at compile time using a novel type system.
In traditional HDLs, signals may unintentionally change when their underlying registers are updated, making it difficult to guarantee the stability of intermediate values across multiple clock cycles. Anvil eliminates this class of errors by making the timing relationships between the creation and use of values explicit, and by enforcing that values are used only when they are semantically valid. At the same time, Anvil gives designers full control over state-storing elements (registers) and cycle-level latency. Anvil compiles to synthesizable SystemVerilog and has demonstrated comparable area, power, and frequency to handwritten SystemVerilog designs in practice, while incurring no additional clock-cycle latency.
You can try Anvil without installation at AnvilHDL Playground, or install it locally by following the Installation Guide guide.
Citation
Anvil has been accepted to apear at ASPLOS 2026. If you use Anvil in your research, please use the following citation:
@article{yu2025anvil,
title={Anvil: A General-Purpose Timing-Safe Hardware Description Language},
author={Yu, Jason Zhijingcheng and Jha, Aditya Ranjan and Mathur, Umang and Carlson, Trevor E and Saxena, Prateek},
journal={arXiv preprint arXiv:2503.19447},
year={2025}
}
Documentation Overview
This documentation is organized as follows:
Language Reference - An up-to-date description of Anvil’s syntax and language features.
Getting Started - A guided tutorial to help you get started with Anvil, including interactive examples and practice problems.
Language Reference