Expressions

Anvil describes hardware behavior through the expression forms below.

• Timing and Bindings
• Conditionals
• Arithmetic and Concatenation
• Communication Expressions
• Functions and Casts
• Generate Expressions

Debug Statements

During simulation, dprint prints messages to the console, much like $display in SystemVerilog. The expression dfinish terminates the simulation. Both expressions are for simulation only.

debug-print ::= "dprint" string-literal "(" expression ")" 
debug-finish ::= "dfinish"